4. Cache Organization and Coherency
The behavior of the processor when executing load and store instructions is determined by the cache algorithm specified for the accessed address. The processor supports five different cache algorithms:
Cache algorithms are specified in three separate places, depending upon the access:
Table 4-1 presents the encoding of the 3-bit cache algorithm field used in the TLB; EntryLo0 and EntryLo1 registers; CP0 Config register K0 field for the kseg0 address space; and VA[61:59] for the xkphys address space.
Table 4-1 Cache Algorithm Field Encodings
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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